BUF5I=BUF5I_0, BUF31TO8I=BUF31TO8I_0, BUF7I=BUF7I_0, BUF6I=BUF6I_0, BUF4TO0I=BUF4TO0I_0
Interrupt Flags 1 Register
| BUF4TO0I | If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 0 (BUF4TO0I_0): No such occurrence 1 (BUF4TO0I_1): Corresponding MB completed transmission/reception |
| BUF5I | If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 0 (BUF5I_0): No such occurrence 1 (BUF5I_1): MB5 completed transmission/reception or frames available in the FIFO |
| BUF6I | If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 0 (BUF6I_0): No such occurrence 1 (BUF6I_1): MB6 completed transmission/reception or FIFO almost full |
| BUF7I | If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 0 (BUF7I_0): No such occurrence 1 (BUF7I_1): MB7 completed transmission/reception or FIFO overflow |
| BUF31TO8I | Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt. 0 (BUF31TO8I_0): No such occurrence 1 (BUF31TO8I_1): The corresponding MB has successfully completed transmission or reception |